Modern integrated circuit (IC) designs often require the design to be implemented with different clock domains. The circuits in these different clock domains often operate at unique clock frequencies in order to fulfill the different data rate requirements. Modern IC designs also often require signals to travel from one clock domain to another clock domain. While it is possible to send signals across different clock domains asynchronously, i.e., assuming the clocks driving the different clock domains are not related in any particular way, it is often not desirable to do so because asynchronous interface requires specialized circuitry that cannot be easily and predictably verified. Synchronous data transfer between clock domains on the other hand can be easily and predictably verified and does require specialized circuitry. It is almost always preferable to design synchronous domain crossings whenever possible.
In order for signals to successfully cross from one domain to another domain based on predicable, synchronous timing relationships, the two clocks driving the two domains must be related to a common base clock. Conventional approach to creating related clocks involves using either phase lock loops (PLLs) or clock dividers. FIG. 1A-B illustrates signals crossing different clock domains in an IC 100 that operate on related clocks. FIG. 1A illustrates related clocks (clock 1 and clock 2 driving clock domains 1 and 2, respectively) that come from different PLLs. Based on the reference clock, PLL 121 produces clock 1 and PLL 122 produces clock 2. Clock 1 directly drives the circuits (e.g., registers/flip-flops) in clock domain 1 while clock 2 directly drives the circuits in clock domain 2. In this instance, clocks 1 and 2 are related because the PLLs 121 and 122 are both operating off the same reference clock 105. Some ICs have PLLs capable of producing multiple, different outputs from a same reference clock. The different outputs of one of these PLLs are also related.
FIG. 1B illustrates related clocks that come from different clock dividers. The clock divider 171 produces clock 1 as a divided clock of the base clock 150, while the clock divider 172 produces clock 2 as a divided clock of the same base clock 150. In this instance, clocks 1 and 2 are related because the clock dividers are operating on a same base clock 150.
Though the different clock domains in FIGS. 1A and 1B are able to communicate synchronously, they are not in a same clock distribution network that is balanced to minimized skew. As a result, the clock skew between clock 1 and clock 2 will be appreciable. The skew between clock 1 and clock 2 makes the timing relationship between the two clock domains less predictable. The skew also limits the clock rates that the circuits in the two clock domains can operate on.
Therefore, there is a need for an IC in which related clock domains can synchronously communicate with each other by utilizing clocks from the same clock distribution network.